In the design of the semiconductor integrated circuit, the pattern layout on the chip area is decided by placing cells or blocks having the logic function or the storing function in the chip and providing the wirings between the input/output terminals to get desired circuit operations. The semiconductor integrated circuit according to the common gate array system is constructed by areas where the cells are placed, areas where the wirings are provided between the cells and the peripheral area where input/output circuits are placed. A plurality of wiring layers are utilized as the wirings on the chip. The wiring layers are allocated to extend in the horizontal/vertical directions in respective layers. The computer optimizes automatically the placement of the cells and the wirings between the terminals and decides the layout pattern on the overall surface of the chip area.
The verifying/correcting process of the layout pattern is executed after the layout pattern is decided. For example, the layout verification is applied to respective patterns such as the cells, the wirings, the vias, and the like placed on the chip area by using softwares such as design rule check (DRC), layout vs schematic (LVS), and the like. Then, the pattern adjusting process such as the optical correction, or the like is executed by using mask data preparation (MDP), optical proximity correction (OPC), and the like.
A dimensional distortion of the layout pattern has a negative effect of a circuit characteristic. Considering the dimensional distortion, a delay computing method in consideration of relationships the process fluctuation of the device and the circuit characteristic is known (see JP-A-11-39357, for example). The logic simulation method to execute the delay analysis in consideration of the mutual delay variation between the signals is known (see JP-A-7-182381, for example). As the method to take the distortion between the design pattern and the pattern manufactured on the wafer into account, the technology to analyze the circuit by preparing correlation data of differences between mask layout widths and finished widths of the wirings and calculating wiring resistance values and wiring capacitance values such that the high-precision wiring finished width can be calculated and the high-precision circuit simulation can be executed is known (see JP-A2001-230323, for example).
However, with the progress of the miniaturization of the dimension of the transistors and the wirings manufactured on the wafer, it becomes difficult to realize the exact layout shape in conformity with the mask pattern. The design pattern that is hard to apply the lithography process not only affects largely the variation in the electrical characteristics of the fine process device structure and the performance/reliability of the semiconductor integrated circuit but also causes short circuit of the wiring, disconnection, etc. to deteriorate the yield. Also, since the distortion is caused between the layout figure intended by the design step and the geometrical figure exposed on the wafer due to the influence of the optical proximity correction, the OPC process applied to correct the distortion becomes complicated. Also, a rapid increase in an amount of data of the in-mask figure representation subsequent to the layout design is caused, and a mask cost is increased. In addition, because the patterns that cannot be handled by the OPC process are generated, the design patterns whose pattern verification/correction steps have been completed must be fed back to the layout design step once again and then such design patterns must be corrected once again in the layout design step.
However, a large feedback loop from the design to the manufacture is generated if the defective patterns found by the lithography verification, or the like is corrected by feeding back such patterns to the layout design. Therefore, a design term is prolonged.